Semiconductor Packaging is progressively driving chip development, and the heterogeneous mix is at the front line of these mechanical advances that are expanding the intricacy of semiconductor plans and testing. To assist with beating this test, chip originators are sending state-of-the-art advancements like enormous information and computerized reasoning (AI) to make testing more proficient and powerful. The Digital Transformation of Electronics Packaging, especially of ICs (Integrated Circuits), Sensors and MEMS (Micro-Electro-Mechanical Systems), MOEMS (Micro-Optoelectronic Mechanical Systems), and Photonics passes on is acquiring and more importance in the present business applications. Particularly for AI, AR/VR, and IoT the presentation, form factor, and cost are huge markers. Scaling down and an expanding level of joining at bundling level targets greater usefulness on less space, which is promising higher framework execution, more modest framework size, and lower framework cost. This requires a framework-level methodology with Chip-Package-Board co-plan and co-improvement with close participation along with the total semiconductor inventory network. Changing Landscape in the Semiconductor Packaging (CLSP) Conference is devoted to uniting countless different academic occasions for show inside the meeting program. Occasions will run throughout a range of time during the gathering relying upon the number and length of the introductions. With its great, it offers an extraordinary benefit for understudies, scholastics and semiconductor’s industry scientists.
The Growing Momentum of Heterogeneous Integration
Challenges for Heterogeneous Integration in Package – Applications
Driving Materials and Processes towards Diversity
Micro Balling on Chips with a High Ball-count for Space Applications
Big Data and Vehicle Analytics
Vehicular Networks
Security and Safety
Active Mold Packaging for Novel Antenna-in-Package Interconnection and Manufacturing
High Throughput & High Yield Heterogeneous Integration with Implemented Metrology for Collective D2W Bonding
High Throughput & High Yield Heterogeneous Integration with Implemented Metrology for Collective D2W Bonding
Heterogeneous Integration Test Impacts
3D Bump Metrology and Inspection
Intelligent Infrastructure and Guidance Systems
Intertwined development of manufacturing processes and test technologies – a prerequisite for future success in advanced packaging
Virtual Prototyping for System-in-Package with Heterogeneous Integration
Processing of new functional materials
Manufacturing process IP
EDA (Electronic Design Automation)
Simulation tools and methods for enhancing SiP
Chip-Package-Board co-design
How can ADK (Assembly Design Kits) be developed and linked to PDK (Process Design Kits) of chip design
Wafer manufacturing technologies
Dr Panagiotis Alevyzakis, Universita degli Studi Guglielmo Marconi, Italy.
September 19, 2024
October 10, 2024
November 18, 2024
December 12 - 13, 2024
Get Connected| Category | Before or on Submission | Before or on Acceptance | After Acceptance |
|---|---|---|---|
| Author (1st paper) | 400 € | 500 € | N/A |
| Non author | 400 € | 500 € | 600 |
| Student (non author) | 400 € | 500 € | 600 |
More details will come soon.
